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International Journal of Engineering and Techniques(IJET) Paper Title : A Pipelined ADC With Sub-ADC Based on Flash–Ramp Architecture

ISSN : 2395-1303
Year of Publication : 2020
10.29126/23951303/IJET-V6I2P9
Authors: -Himanshu Shekhar, Dr Bharti Chourasia

         



MLA Style: Himanshu Shekhar, Dr Bharti Chourasia A Pipelined ADC With Sub-ADC Based on Flash–Ramp Architecture " Volume 6 - Issue 2(1-6) March - April,2020 International Journal of Engineering and Techniques (IJET) ,ISSN:2395-1303 , www.ijetjournal.org

APA Style: Himanshu Shekhar, Dr Bharti Chourasia A Pipelined ADC With Sub-ADC Based on Flash–Ramp Architecture " Volume 6 - Issue 2(1-6) March - April,2020 International Journal of Engineering and Techniques (IJET) ,ISSN:2395-1303 , www.ijetjournal.org

Abstract
This work is base on the pipeline ADCs architecture. Pipeline ADCs are convenient alternatives to time interleaving. As the stage of the pipeline is simpler asd compare to a full converter, the design area and power are competitive. The pipeline ADC design with two or more stages in which every stage is of a low resolution ADC, and combining these stages results in a higher resolution.The design ADC consists of channels for high operating speed and every channel consist of a pipelined flash and ramp analog 5to digital converter architecture with reduce power and a optimize area. The sample ADC design in a 50-nanometer CMOS technology with 8-bit of resolution. The supply voltage is 1.2V

Reference
[1] Dante Gabriel Muratͦ ore, Edoardo Boͦ ͦ ͦ ͦ nizzoni, Franco Maloberti "A Pipeline ADC for Very High Conversioͦn Rates" IEEE coͦnference Proceeding Internatioͦnal Symposium on Circuits and Systems (ISCAS) IMS University Montreal, QC, Canada Year 22-25 May 2016. [2] Young-Deͧuk Jeon, Jae-W ͦ on Nam, Kwi-Doͦng Kim, Tae Mͦ oon Roh, and Joͦng-Kee Kwon "A DualChannel Pipelined ADC With Sͧ ub-ADC Based on Flash–SAR Architecture" IEEE Transactions On Circuits And Systems—II: Express Briefs, Vol. 59, No. 11, November 2012 ϸϸ no. 741-745. [3] D.Y. Chang, C. Munoz, D. Daly, S.K. Shin, K. Guay, T. Thͧ urston,˜ H.S. Lee, K. Gulati, M. Straayer, “A 21mW 15b 48MS/s Zero-Crͦ ͦ ͦͦͥ ossing Pipeline ADC in 0.13µm CMOS with 74dB SNDR”, IEEE International Solid Stͣ ate Circuits Conference (ISSCC) Dig. Tech. Pap., ϸϸ. 204-205, 2014. [4] N. Dͦ olev, M. Kramer, B. Muͧ rmann, “A 12-bit, 200-MS/s, 11.5-mW Pipeline ADC uͧ sing a Pulsed Bucket Brigade Front-End”, IEEE Symposium on VLSI Circuits Dig. Tech. Pap., pp. C98-C99, 2013. [5] B. Hershberg, S. Wͤ eaver, K. Sobue, S. Takeuchi, K. Hamashita, U.K. Moͦon, “Ring Amplifiers for Switched Capacitor Circuits”, IEEE Journal of Solid State Circuits, vol. 47, ϸϸ. 2928- 2942, Dec. 2012. [6] D.G. Mͧ uratore, A. Akdikmen, F. Maloberti, “Very high-speed CMOS comparators for multiGS/s A/D converters”, Proc. of the IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), ϸϸ. 240-243, 2015.

Keywords
Flash ADC, Ramp ADC, Pipelined, SAR, Dual Slop

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