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Paper Title : Power Reduction of Domino Logic with clock gating using 16nm CMOS Technology
ISSN : 2395-1303
Year of Publication : 2022
MLA Style: -Bhukya Naveen Kumar, Dr. V. Sudheer Raja Power Reduction of Domino Logic with clock gating using 16nm CMOS Technology , Volume 8 - Issue 5 September - October 2022 International Journal of Engineering and Techniques (IJET) ,ISSN:2395-1303 , www.ijetjournal.org
APA Style: - Bhukya Naveen Kumar, Dr. V. Sudheer Raja Power Reduction of Domino Logic with clock gating using 16nm CMOS Technology , Volume 8 - Issue 5 September - October 2022 International Journal of Engineering and Techniques (IJET) ,ISSN:2395-1303 , www.ijetjournal.org
In this paper, a new technique of power reduction in CMOS domino logic is proposed. The proposed technique uses clock gating as well as output hold circuitry. Clock is passed to the domino logic only during the active state of the circuit. During standby mode, clock is bypassed while the state of the circuit is retained. A 2:1 multiplexer is used for clock gating and for retaining the state of the circuit. Simulation results are being carried out in a 2-input NAND gate, 2-input nor gate and 1-bit conventional full adder cell in 16nm CMOS technology. The power of the proposed circuit is reduced to an average of 99.37 % with respect to standard domino logic. Propagation delay is slightly increased to an average of 4.53 %. Area of the proposed circuit increases to four transistors per domino module.
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— Dynamic, Domino, static power, clock gating, CMOS.